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? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 1 ? description the ace24c128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable r ead-only memory (eeprom) organized as 16,384/32,768 words of 8 bits each. the device?s casc adable feature allows up to 8 devices to share a common two-wire bus. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. features z low operation voltage: vcc = 1.7v to 5.5v z internally organized: 16,384 x 8(128k), 32,768 x 8(256k) z two-wire serial interface z schmitt trigger, filtered inputs for noise suppression z bi-directional data transfer protocol z 1mhz (2.5v~5.5v) and 400 khz (1.7v) compatibility z write protect pin for hardware data protection z 64-byte page write modes (partial page writes are allowed) z self-timed write cycle (5 ms max) z high-reliability - endurance: 1,000,000 write cycles - data retention: 100 years z pdip-8,sop-8,tssop-8 rohs compliant packages z wafer sales: available in inked wafer form absolute maximum ratings operating temperature -55 to +125 storage temperature -65 to +150 voltage on any pin with respect to gr ound -1.0v to +7.0v maximum operating voltage 6.25v dc output current 5.0 ma *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at thes e or any other conditions beyon d those indicated in the operat ional sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 2 packaging type pin configurations pin name function a0~a2 device address inputs sda serial data input / output scl serial clock input wp write protect vcc power supply gnd ground
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 3 block diagram figure 1
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 4 ordering information selection guide ace24c128/256 xx + x h serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bi-directional for serial data trans fer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open-collector devices. device/page addresses (a2, a1, a0): the a2, a1 and a0 pins are device address inputs that are hardwired or left not co nnected for hardware compatibility with other ace24cxxx/ace24cxx x devices. when the pins are hardwired, as many as eight 128k/256k devices may be addr essed on a single bus system (device addressing is discussed in detail under the device addressing section).if the pins are left floating, the a2, a1 and a0 pins will be internally pulled down to gnd if the capacitive coupling to the circuit board vcc plane is < 3pf, if coupling is > 3pf recommends connecting the address pins to gnd. write protect (wp): the ace24c128/256 has a write provides hardware data protection. the wp pin allows normal write operations when connected to ground (gnd). when the write protect pin is connected to vcc. all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled is < 3pf , if coupling is > 3pf, recommends connecting the pins to gnd. switching wp to vcc prior to a write operation creates a software write protected function. write protect description part of the array protected wp pin status ace24c128 ACE24C256 wp=v cc full (128k) memory full (256k) memory wp=gnd normal read/write operations pb - free u : tube t : tape and reel dp : pdip-8 fm : sop-8 tm : tssop-8 halo g en-free
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 5 memory organization ace24c128, 128k serial eeprom: internally organized with 256 pages of 64 bytes each, random word addressing requires a 14-bit data word address. ACE24C256, 256k serial eeprom: internally organized with 512 pages of 64 bytes each, random word addressing requires a 15-bit data word address. pin capacitance applicable over recommended operating range from: t a = 25 , f = 1.0 mhz, v cc = +1.8v. symbol test condition max units conditions c i/o 1 input / output capacitance 8 pf v i/o = 0v c in 1 input capacitance 6 pf v in = 0v note: 1. this parameter is characterized and is not 100% tested. dc characteristics applicable over recommended operating range from: t a = -40 to +85 , v cc = +1.7v to +5.5v, (unless otherwise noted). symbol parameter test condition min typ max units v cc supply voltage 1.7 5.5 v i cc1 supply current v cc = 5v, read at 400khz 0.4 1.0 ma i cc2 supply current v cc = 5v, write at 400khz 2.0 3.0 ma i sb1 standby current v cc = 1.7v, v in = v cc / v ss 1.0 a i sb2 standby current v cc = 5.5v, v in = v cc / v ss 6.0 a i li input leakage current v in = v cc /v ss 0.10 3.0 a i lo output leakage current v out = v cc / v ss 0.05 3.0 a v il 1 input low level -0.6 v cc x0.3 v v ih 1 input high level v cc x0.7 v cc +0.5 v v ol2 output low level 2 v cc = 3.0v, i ol = 2.1 ma 0.4 v v ol1 output low level 1 v cc = 1.7v, i ol = 0.15 ma 0.2 v note: 1. v il min and v ih max are reference only and are not tested.
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 6 ac characteristics applicable over recommended operating range from: t a = -40 to +85 , v cc = +1.7v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted). test conditions are listed in note2. 1.7-volt 2.5-volt 5.5-volt symbol parameter min max min max min max units f scl clock frequency, scl 400 1000 1000 khz t low clock pulse width low 1.3 0.40 0.4 s t high clock pulse width high 0.6 0.40 0.4 s ti 1 noise suppression time 100 50 50 t aa clock low to data out valid 0.1 0.9 0.05 0.55 0.05 0.55 s t buf 1 time the bus must be free before a new transmission can start 1.3 0.5 0.5 s t hd.sta start hold time 0.6 0.25 0.25 s t su.sta start setup time 0.6 0.25 0.25 s t hd.dat data in hold time 0 0 0 s t su.dat data in setup time 100 100 100 ns t r inputs rise time 0.3 0.3 0.3 s t f inputs fall time 300 100 100 ns t su.sto stop setup time 0.6 0.25 0.25 s t dh data out hold time 50 50 50 ns t wr write cycle time 5 5 5 ms endurance 1 5.0v, 25 , page mode 1,000,000 write cycles notes:1. this parameter is characterized and not 100% tested. 2.ac measurement conditions: rl (connects to vcc): 1.3k input pulse voltages: 0.3 vcc to 0.7 vcc input rise and fall times: Q 50 ns input and output timing reference voltages: 0.5vcc
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 7 device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (refer to figure 4). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to figure 5). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a st andby power m ode (refer to figure 5). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowledge that it has received each word. standby mode : the ace24c128/256 features a low-power standby mode which is enabled: (a) u pon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. memory reset : after an interruption in protocol power loss or system rese t, any two-wire part can be protocol reset by following these steps: 1. clock up to 9 cycles. 2. look for sda high in each cycle while scl is high and then. 3. create a start condition as sda is high. bus timing figure 2 scl: serial clock, sda: serial data i/o
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 8 write cycle timing figure 3 scl: serial clock, sda: serial data i/o note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. figure 4 data validity figure 5 start and stop definition figure 6 output acknowledge
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 9 device addressing the 128k/256k eeprom device require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to figure 7). the device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. this is common to all the eeprom devices. the 128/256k eeprom use the thre e device address bits a2, a1, a0 to allow as many as eight devices on the same bus. these bits must compare to their corresponding hard-wired input pins. the a2,a1 and a0 pins use an internal proprietary circuit th at biases them to a logic low condition if the pins are allowed to float. the eight bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the device will return to a standby state. noise protection: special internal circuitry place on the sda and scl pins prevent small noise spikes from activating the device. date security: the ace24c128/256 has a hardware data protect scheme that slows the user to write protect the entire memory when the wp pin is at vcc. write operations byte write: a write operation requires two 8-bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr, to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (refer to figure 8). page write: the 128k/256k eeprom is capable of an 64-byte page write. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition (refer to figure 9). the data word address lower five bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten.
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 10 acknowledge polling: once the internally timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero allowing the read or write sequence to continue. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page to the first byte of the first page. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is se rially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condition (refer to figure 10). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a foll owing stop condition (refer to figure 11). sequential read: sequential reads are initiated by either a curren t address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit (256k) is reac hed, the data word address will ?roll over? and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to figure 12). 1 0 1 0 a 2 a 1 a 0 r/w msb lsb figure 7 device address
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 11 figure 8 byte write figure 9 page write figure 10 current address read
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 12 figure 11 random read figure 12 sequential read
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 13 packaging information pdip-8 note: dimensions in millimeters.
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 14 sop-8 note: dimensions in millimeters.
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 15 tssop-8 note: dimensions in millimeters.
? ??????????????????????????????????????????????????????????????? ??????????? ace24c128/256 ??????????????????????? technology two-wire serial eeprom ver 1.2 16 notes ace does not assume any responsibility for use as cr itical components in life support devices or systems without the express written approval of the president and general counsel of ace electronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace-ele.com/

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